Method for testing memory device and test system

ABSTRACT

A method for testing a memory device includes the following steps of: generating a first refresh command to the memory device; storing a first refresh address information into a register of the memory device according to the first refresh command; reading out the first refresh address information according to a mode register read command; comparing the first refresh address information with an expectation address information to generate a comparison result; and generating a second refresh command to the memory device or screening out the memory device according to the comparison result.

BACKGROUND Field of Invention

The present disclosure relates to an electronic system and a method.More particularly, the present disclosure relates to a test system and amethod for testing a memory device.

Description of Related Art

Each of conventional memory devices is composed of a plurality of memorycells. Memory cells are composed of capacitors. Memory devices have aleakage current due to process problems. Therefore, memory devicesshould be accessed a refresh command to protect data stored in memorycells periodically. However, due to memory cell property and test cost,memory devices are usually configured to verify a refresh command at alow speed and a high temperature.

For the foregoing reason, there is a need to provide some other a methodfor testing a memory device to solve the problems of the prior art.

SUMMARY

One aspect of the present disclosure provides a method for testing amemory device. The method for testing the memory device includes thefollowing steps of: generating a first refresh command to the memorydevice; storing a first refresh address information into a register ofthe memory device according to the first refresh command; reading outthe first refresh address information according to a mode register readcommand; comparing the first refresh address information with anexpectation address information to generate a comparison result; andgenerating a second refresh command to the memory device or screeningout the memory device according to the comparison result.

Another aspect of the present disclosure provides a test system. Thetest system includes a test equipment and a memory device. The testequipment is configured to generate a first refresh command and a moderegister read command. The memory device is coupled to the testequipment. The memory device includes a register and a refresh circuit.The register is configured to store a first refresh address informationaccording to the first refresh command. The refresh circuit is coupledthe register. The refresh circuit is configured to read out the firstrefresh address information according to the mode register read command.The test equipment is configured to compare the first refresh addressinformation with an expectation address information to generate acomparison result. The test equipment is configured to generate a secondrefresh command to the memory device or screening out the memory deviceaccording to the comparison result.

These and other aspects of the present disclosure will become apparentfrom the following description of the preferred embodiment taken inconjunction with the following drawings, although variations andmodifications therein may be effected without departing from the spiritand scope of the novel concepts of the disclosure.

It is to be understood that both the foregoing general description andthe following detailed description are by examples, and are intended toprovide further explanation of the present disclosure as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention can be more fully understood by reading the followingdetailed description of the embodiment, with reference made to theaccompanying drawings as follows:

FIG. 1 depicts a schematic diagram of a test system according to oneembodiment of the present disclosure; and

FIG. 2 depicts a flow chart of a method for testing a memory deviceaccording to one embodiment of the present disclosure.

DETAILED DESCRIPTION

Reference will now be made in detail to the present embodiments of theinvention, examples of which are illustrated in the accompanyingdrawings. Wherever possible, the same reference numbers are used in thedrawings and the description to refer to the same or like parts.

FIG. 1 depicts a schematic diagram of a test system 1000 according toone embodiment of the present disclosure. In some embodiments, the testsystem 1000 includes a memory device 1100 and a test equipment 1200. Thememory device 1100 is coupled to the test equipment 1200. The memorydevice 1100 includes a refresh circuit 1110 and a register 1120. Therefresh circuit 1110 is coupled to the register 1120.

In some embodiments, the test equipment 1200 is configured to generate afirst refresh command and a mode register read command. The memorydevice 1100 is coupled to the test equipment. The register 1120 isconfigured to store a first refresh address information according to thefirst refresh command. The refresh circuit 1110 is configured to readout the first refresh address information according to a mode registerread command. The test equipment 1200 is configured to compare the firstrefresh address information with an expectation address information togenerate a comparison result. The test equipment 1200 is configured togenerate a second refresh command to the memory device 1100 or screenout the memory device 1100 according to the comparison result.

In some embodiments, the memory device 1100 includes dynamic randomaccess memories (DRAM). In some embodiments, the memory device 1100 iscomposed of a plurality of memory cells. The plurality of memory cellsare arranged in rows and columns.

In some embodiments, the refresh circuit 1110 is configured to refreshmemory cells of one of rows of the memory device 1100 to generate arefresh address information according to a refresh command.

In some embodiments, the refresh circuit 1110 includes a refresh counter1111. The refresh counter 1111 is configured to count a number of testloops that generate refresh commands.

In some embodiments, in order to facilitate the understanding of atesting system 1000 for testing the memory device 1100 shown in FIG. 1 .Please refer to FIG. 1 and FIG. 2 . FIG. 2 depicts a flow chart of amethod 200 for testing a memory device 1100 according to one embodimentof the present disclosure. In some embodiments, the method 200 fortesting a memory device includes step 210 to step 260, which will bedescribed as shown below.

In step 210, a first refresh command is generated to the memory device.In some embodiments, please refer to FIG. 1 and FIG. 2 , a first refreshcommand and a mode register read command are generated into the refreshcircuit 1110 of the memory device 1100 by the test equipment 1200.

In step 220, a first refresh address information is stored into aregister of the memory device according to the first refresh command. Insome embodiments, please refer to FIG. 1 and FIG. 2 , a first refreshaddress information is stored according to the first refresh command bythe register 1120.

In some embodiments, the refresh circuit 1110 is configured to receivethe first refresh command. The refresh circuit 1110 is configured torefresh memory cells of one of rows of the memory device 1100 so as togenerate the first refresh address information according to the firstrefresh command. The refresh circuit 1110 is configured to transmit thefirst refresh address information into the register 1120 for storing.

It should be noted that the refresh circuit 1110 is configured to readone row at one time according to one refresh command. In other words,each of refresh commands means a different signal. To furtherillustrate, memory refreshing is a process of periodically readinginformation from an area of the memory device 1100 and immediatelyrewriting the read information to the same area without modification.

In step 230, the first refresh address information is read out accordingto a mode register read command.

In some embodiments, please refer to FIG. 1 and FIG. 2 , a mode registerread command is generate to the refresh circuit 1110 of the memorydevice 1100 by the test equipment 1200. The refresh circuit 1110 isconfigured to read out the first refresh address information from theregister 1120 according to the mode register read command. The refreshcircuit 1110 is configured to output the first refresh addressinformation via an I/O output pad to the test equipment 1200 withoutpassing the refresh counter 1111.

In step 240, the first refresh address information is compared with anexpectation address information.

In some embodiments, please refer to FIG. 1 and FIG. 2 , the firstrefresh address information is compared with an expectation addressinformation to generate a comparison result by the test equipment 1200.In some embodiments, the expectation address information is stored inthe test equipment 1200.

It is noted that each of rows of the memory device 1100 has differentkinds of refresh address information, and the test equipment 1200already has different kinds of expectation address informationcorresponding to each of rows.

For example, the memory device 1100 has 16 rows. After a process ofmemory refreshing, the memory device 1100 is configured to generate 16kinds of refresh address information corresponding to each of the 16rows. The test equipment 1200 already has 16 kinds of expectationaddress information corresponding to each of the 16 rows. The testequipment 1200 is configured to compare whether the 16 kinds of refreshaddress information are the same as the 16 kinds of expectation addressinformation.

In some embodiments, the step 250 is executed if the comparison resultis that the first refresh address information is the same as theexpectation address information by the test equipment 1200.

In some embodiments, the step 260 is executed if the comparison resultis that the first refresh address information is different from theexpectation address information by the test equipment 1200.

In step 250, a second refresh command is generated to the memory device.In some embodiments, please refer to FIG. 1 and FIG. 2 , a secondrefresh command is generated to the memory device 1100 according to thecomparison result by the test equipment 1200. The comparison result isthat the first refresh address information is the same as theexpectation address information. In other words, one of rows of thememory device 1100 is normal. Therefore, the test equipment 1200 isconfigured to generate a different refresh command so as to test anotherone of rows of the memory device 1100.

In step 260, the memory device is screened out. In some embodiments,please refer to FIG. 1 and FIG. 2 , the memory device 1100 is screenedout according to the comparison result by the test equipment 1200. Thecomparison result is that the first refresh address information isdifferent from the expectation address information. In other words, oneof rows of the memory device 1100 is broken. The memory device 1100needs to be screened out. In some embodiments, the aforementioned steps210 to 240 can be executed repeatedly.

Based on the above embodiments, the present disclosure provides a method200 for testing a memory device 1100 and a test system 1000 to store arefresh address information into a register 1120 at first so as to allowmemory device 1100 to verity refresh commands at a high speed and a lowtemperature.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of the presentinvention without departing from the scope or spirit of the invention.In view of the foregoing, it is intended that the present inventioncover modifications and variations of this invention provided they fallwithin the scope of the following claims.

What is claimed is:
 1. A method for testing a memory device, comprising:generating a first refresh command to the memory device; storing a firstrefresh address information into a register of the memory deviceaccording to the first refresh command; reading out the first refreshaddress information according to a mode register read command; comparingthe first refresh address information with an expectation addressinformation to generate a comparison result; and generating a secondrefresh command to the memory device or screening out the memory deviceaccording to the comparison result.
 2. The method for detecting thememory device of claim 1, wherein the memory device comprises a dynamicrandom access memory (DRAM).
 3. The method for detecting the memorydevice of claim 1, wherein the first refresh command is different fromthe second refresh command.
 4. The method for detecting the memorydevice of claim 1, wherein generating the first refresh command to thememory device comprises: refreshing memory cells of one of rows of thememory device to generate the first refresh address informationaccording to the first refresh command.
 5. The method for detecting thememory device of claim 1, wherein generating the second refresh commandto the memory device or screening out the memory device according to thecomparison result comprises: generating the second refresh command tothe memory device if the comparison result is that the first refreshaddress information is a same as the expectation address information. 6.The method for detecting the memory device of claim 5, whereingenerating the second refresh command to the memory device or screeningout the memory device according to the comparison result furthercomprises: screening out the memory device if the comparison result isthat the first refresh address information is different from theexpectation address information.
 7. The method for detecting the memorydevice of claim 1, wherein the expectation address information is storedin a test equipment.
 8. The method for detecting the memory device ofclaim 1, wherein reading out the first refresh address informationaccording to the mode register read command comprises: generating themode register read command to the memory device so as to output thefirst refresh address information via an I/O output pad.
 9. A testsystem, comprising: a test equipment, configured to generate a firstrefresh command and a mode register read command; and a memory device,coupled to the test equipment, wherein the memory device comprises: aregister, configured to store a first refresh address informationaccording to the first refresh command; and a refresh circuit, coupledthe register, and configured to read out the first refresh addressinformation according to the mode register read command; wherein thetest equipment is configured to compare the first refresh addressinformation with an expectation address information to generate acomparison result, wherein the test equipment is configured to generatea second refresh command to the memory device or screening out thememory device according to the comparison result.
 10. The test system ofclaim 9, wherein the memory device comprises a dynamic random accessmemory (DRAM).
 11. The test system of claim 9, wherein the first refreshcommand is different from the second refresh command.
 12. The testsystem of claim 9, wherein the refresh circuit is configured to refreshmemory cells of one of rows of the memory device to generate the firstrefresh address information according to the first refresh command. 13.The test system of claim 9, wherein the test equipment is furtherconfigured to generate the second refresh command to the memory deviceif the comparison result is that the first refresh address informationis a same as the expectation address information.
 14. The test system ofclaim 13, wherein the test equipment is further configured to screen outthe memory device if the comparison result is that the first refreshaddress information is different from the expectation addressinformation.
 15. The test system of claim 9, wherein the refresh circuitcomprises a refresh counter, wherein the refresh counter is configuredto count a number of test loops that generate the first refresh commandand the second refresh command.